Memory Contexts: Supporting Selectable Cache and TLB Contexts
نویسندگان
چکیده
In this paper I argue that in addition to supporting multiple cores, future microprocessor designs should decouple cores from caches and TLBs and support multiple, run-time selectable hardware memory contexts per core. Multiple memory contexts would allow the operating system and other threads to run without polluting each others’ cache and TLB contexts, reduce coherence traffic, and enable better informed scheduling decisions, thus reducing execution times. In addition, it add provide significant flexibilty and benefits to virtualized environments.
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